1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory devices, and particularly to a nonvolatile semiconductor multi-valued memory device in which one unit of data is formed by a group of memory cells (hereinafter simply referred to as "cells") each having a transistor whose threshold voltage can be set at multiple values. The present invention also relates to a method for reading data from the nonvolatile semiconductor memory device and a method for writing data into the nonvolatile semiconductor memory device.
2. Description of the Background Art
A conventional nonvolatile semiconductor multi-valued memory device is disclosed in Japanese Patent Application Laid-Open No.9-91971 (1997), for example. FIGS. 9A to 9D are diagrams used to explain a method for writing data into the conventional nonvolatile semiconductor multi-valued memory device described in the reference. FIGS. 9A to 9D show an example in which four MOS transistors 101 to 104 are connected to one word line W and four cells C1 to C4 form a unit of data. The MOS transistors 101 to 104 each have a control gate and a floating gate, where the threshold voltage Vth can be set at four values Vth1 to Vth4 (Vth1&lt;Vth2&lt;Vth3&lt;Vth4) according to the amount of charge exiting in the floating gate. Its writing operation is now described in an example in which the threshold voltages Vth of the MOS transistors 101, 102, 103 and 104 are set at Vth4, Vth3, Vth2 and Vth1, respectively.
First, as shown in FIG. 9(A), the threshold voltages Vth of the MOS transistors 101 to 104 are all set at the highest value Vth4. At this time, electrons are sufficiently stored in the floating gates of the MOS transistors 101 to 104. Next, as shown in FIG. 9(B), a given amount of electrons are discharged from the floating gates of the MOS transistors 102 to 104 to set the threshold voltages Vth of the MOS transistors 102 to 104 at Vth3, which is followed by a verification. Next, as shown in FIG. 9(C), a given amount of electrons are discharged from the floating gates of the MOS transistors 103 and 104 to set the threshold voltages Vth of the MOS transistors 103 and 104 at Vth2, which is followed by a verification. Finally, as shown in FIG. 9(D), a given amount of electrons are discharged from the floating gate of the MOS transistor 104 to set the threshold voltage Vth of the MOS transistor 104 at Vth1, which is followed by a verification.
FIG. 10 is a diagram used to explain a method for reading data from the conventional nonvolatile semiconductor multi-valued memory device described in the reference mentioned above. In the reading operation in the conventional nonvolatile semiconductor multi-valued memory device, an MOS transistor whose threshold voltage Vth is in the range of V6 or higher is regarded as an MOS transistor having the threshold voltage Vth4, an MOS transistor whose threshold voltage Vth is in the range of V4 to V5 is regarded as an MOS transistor having the threshold voltage Vth3, an MOS transistor whose threshold voltage Vth is in the range of V2 to V3 is regarded as an MOS transistor having the threshold voltage Vth2, and an MOS transistor whose threshold voltage Vth is in the range of V1 or lower is regarded as an MOS transistor having the threshold voltage Vth1.
As explained above, the conventional nonvolatile semiconductor multi-valued memory device manages and controls the threshold voltages of a plurality of MOS transistors by using the absolute voltage values (absolute values) Vth1, Vth2, Vth3 and Vth4 (or V1, V2, V3, V4, V5 and V6). When a plurality of MOS transistors are formed on a chip, all MOS transistors do not have completely the same physical characteristics; actually, there are variations in characteristics among the MOS transistors. Accordingly, some MOS transistors are quick at writing (that is to say, for the same writing stress, some MOS transistors allow a larger amount of charge to be discharged from or injected into the floating gate than other MOS transistors, so that the threshold voltage shifts more largely) and some MOS transistors are slow at writing.
Accordingly, as in the conventional nonvolatile semiconductor multi-valued memory device, controlling the threshold voltages of a plurality of MOS transistors having different characteristics by using absolute voltage values requires repeating the above-described flow of: with the write time divided into a plurality of small unit times, applying a given write stress to shift the threshold voltages for each small unit time, verifying the threshold voltages each time, and applying a write stress again if the threshold voltages have not attained a defined range. The conventional nonvolatile semiconductor multi-valued memory device thus has the problem that the processing takes time especially in data writing operation.
In the nonvolatile semiconductor multi-valued memory devices, it is possible to increase the storage capacity per unit area (i.e. storage density) by increasing the number of multiple values of each MOS transistor. However, when the number of multiple values of the MOS transistors is increased in the above-described conventional nonvolatile semiconductor multi-valued memory device, the writing operation takes a still longer time and the threshold voltage of the MOS transistors must be divided into a larger number of smaller ranges, leading to processing speed reduction and accuracy reduction in data processing. It is then difficult to enhance the storage density by using multiple-valued MOS transistors.